The present invention is related to one time programmable devices, and is more particularly related to a non-destructive method and its circuit for use in determining the programmability of a one time programmable device.
One time programmable devices containing a plurality of memory cells or bits in a memory array, and in which each bit may be individually programmed by a user, are well known. One important consideration in the design of one time programmable devices is the probability of future programming of such devices. The best way to test programmability of these devices is to actually program each memory cell. However, this renders the devices useless. Any test procedure which measures parameters known to correlate statistically with future bit programmability can dramatically impact final programming yield and customer satisfaction with the product. For instance, it has been found that if the individual bit programmability of a sample of 64K devices can be improved from 99.999% to 99.9999% (an improvement of 9.times.10.sup.-4 %) the resultant increase in programming yield will be over 41%.
U.S. Pat. No. 4,488,262 by Basire et al., issued Dec. 11, 1984 for "Electronically Programmable Read Only Memory," discloses a one time programmable read only memory device wherein each memory cell is formed of a bipolar transistor provided with a base region and an emitter region covered with a dielectric layer. When the cell is in its initial condition it represents a binary 0 information bit. The application of approximately 4 volts causes the dielectric layer to break down, and places the bit line in ohmic contact with the emitter, which sets the cell in its second condition representing a binary 1 information bit.
U.S. Pat. No. 4,418,403 by O'Toole et al., issued Nov. 29, 1983 for "Semiconductor Memory Cell Margin Test Circuit," discloses a semiconductor memory cell test circuit for testing the operating margin of semiconductor memory cells without affecting the operation of the peripheral circuits which read or write the memory cell being tested.
U.S. Pat. No. 4,459,694 by Ueno et al., issued July 10, 1984 for "Field Programmable Device With Circuitry For Detecting Poor Insulation Between Adjacent Word Lines," discloses a circuit for testing for poor insulation between word lines in a field programmable memory device.